Fault-tolerant programmable logic array for nanoelectronics

SUMMARY

This paper presents the architecture for a nanoelectronic logic system in which a regular array of logic gates with programmable interconnections is accompanied by a data transmitter and receiver as well as program registers and a controller. Binary programmable interconnections assure system versatility by providing the means of computing different logic operations. They also allow setting the redundancy level via the number of columns clustered to compute a certain function. A system operation is explained and visualized with a number of examples. The embedded scheme of fault tolerance can effectively mitigate permanent, as well as transient, faults. Some implementation and performance aspects are approached through simulations of single-electron tunneling structures. However, the proposed architectural concept is generic and can be applied to systems implemented with alternative nanotechnologies. Copyright © 2012 John Wiley & Sons, Ltd.

An architecture for nanoelectronic logic system is presented, in which regular array of nanoscale logic gates is accompanied by CMOS control circuitry. Binary programmable interconnections provide means of computing different logic operations. They also allow for setting the redundancy level via the number of columns clustered to compute a certain function. The embedded fault-tolerance scheme can effectively mitigate permanent as well as transient faults. The proposed architectural concept is generic and can be applied to systems implemented with alternative nanotechnologies.